What’s new in GENIO^TM 1.7

GENIO^TM 1.7 saves even more design time than previous version, because it now tracks and classifies potential design process issues.

Using a dedicated always-on dock, GENIO^TM 1.7 alerts designers to a full list of problems classified by severity, scope, and category. This extensive check provides a real-time update after any operation and new violations will be added to the “Issues Dock”.

Select an issue in the dedicated dock and all errors and warning are highlighted with a severity-driven colour across the GUI and the 2D/3D design views.

GENIO^TM 1.7 performs several categories of checks. Key among them are checks on placement rules during floor planning to catch violations such as overlapping instances, out of boundary placement, and ignored keep-out zones.

Other checks spot vertical routing connectivity issues such as broken nets and crossing fly lines.

GENIO^TM Version 1.6 crosses the entire GENIO^TM family and updates. GENIO 2D, GENIO 2.5D and GENIO 3D co-design tools. Now, every GENIO^TM tool includes Parasitic Estimation and Stack Planning functionality to further slash total design time and reduces overall design complexity.

Parasitic Estimation enhances GENIO^TM’s time-to-design superiority.  This function enables early-on system analysis, based on virtual routes, prior to physical implementation. Parasitic Estimation is usually implemented after a chiplet-based system design and its system-level interconnects have optimized end-to-end 3D-aware signal assignment.

GENIO^TM produces a pre-routing Parasitic Estimations report, based on Manhattan distances and coupled with RC and TSV/bump/C4/balls contributions, to enable early-on Static Timing Analysis.  The key value is the ability to conduct static timing analysis during system exploration without waiting the results of the lengthy detailed physical routing process.

The Stack Planning Support helps designers automatically identify the best possible 3D stack configuration, given physical and electrical constraints. The new floor planning methodology provides a more efficient chiplet-based 3D-IC system organization, optimizing electrical performances and reducing the physical resources (TSVs) required for vertical interconnect.

Stack Planning provides a detailed comparison of multiple floor planning scenarios that allow the early comparison of multiple architecture configurations. Floor plan configurations are tagged and compared. Connectivity Status dialog displays net lengths/statistics and can be filtered by Net Name, Net Group, path, sub-paths. 3D stack planning features are specifically designed to setup system initial configuration, improve exploration of all possible configurations, optimize and compare the most promising ones and suggests the optimal final solution.

Below examples of 3D Stack Planning Interconnect Optimization on Selected Configurations.