HIPER is an ambitious technical development project, leading to a novel solution to support the future demands of next generation electronic products, based on four beyond state-of-the-art innovations:

  1. Holistic design environment: HIPER is application and technology agnostic and ease the integration of emerging heterogeneous 2D 2.5D and 3D systems. It provides a concurrent design flow across design discipline.
  2. First Time Right: Hiper drives from concept to design  avoiding entering “dead-end” architectures/design roads by enabling system level exploration across architectures to identify the more efficient & cost effective one.
  3. Cross-Hierarchical 3D-aware pathfinding to automate the optimization of up to hundreds of thousands of connections –including optical to electrical interconnect- while reducing the number of physical resources needed for implementation.
  4. Novel design approach: HIPER creates never-before-seen levels of IC system integration that shorten the design cycle by two orders of magnitude, drive faster time-to-manufacturing, improve yields and streamlines the entire IC eco-system to enable function-intensive IC-designs that will be the backbone for the most advanced next-generation integrated circuits. It adds unique features to enhance any third-party design implementation flow from initial design to manufacturing.

HIPER is the underlying technology of the GENIO Product Suite.

The HIPER Technology
  • provides package, silicon interposer and die co-design features that are key to achieve the area, power and performance targets, without being overwhelmed by the complexity of dealing with horizontal and vertical interconnects
  • can be integrated with all the existing commercial EDA platforms via standard formats
  • enables a smooth integration with custom flows/tools via a plug-in mechanism
  • deals with system constraints, both ways: top-down (die-driven) and bottom-up (package-driven)
  • offers an I/O optimization interface from which the cross-fabric communication structures can be created and optimized
  • allows the designer to quickly run “what-if analysis”: exploration of several different configurations and selection of the best one, in order to reduce the total wire length and crossings (what-if analysis)
  • brings extreme flexibility as its optimization algorithms can be customized according to the specific design requirements
System architecture

HANOI Project was used to develop two building blocks that are the foundation of the HIPER technology: the co-design platform and its GUI.

The HANOI design platform provides a common, cross-fabric, environment to represent all the levels of complex, 2D-2.5D-3D system designs: multiple and heterogeneous components (one or more die, silicon interposer, package and even PCB portions), their connectivity, and physical/electrical design constraints.

A GUI (Graphic User Interface) is made available to the designer. From there the cross-fabric structures can be created from scratch or incrementally imported and stored in a common database. Thanks to its speed and automation functionalities, HANOI facilitates the system architects to create a quick preview of the design to be explored, modified, compared, optimized exploiting HIPER functionalities and optimization engines.

The Hanoi GUI

The Graphic User interface has been designed to be user friendly and to deliver all the cross discipline functionalities that are needed by the system architect, ALL profile of designers (IC, package and PCB) not to mention assembly and testing engineers.

The patented cross-hierarchical pathfinding optimization engine, enables a 3D-aware optimization, seeking for the best routing path across the entire system hierarchy, in one single run. The optimization is constraint driven: user can fine tune standard constraints and/or create custom, project specific, ones.

HIPER I/O Planning & Optimization technology

HIPER “I/O Planning & Optimization” technology facilitates all the design cycle from feasibility analysis down to dataset creation to drive physical implementation and incremental optimization of connectivity. Handling hundreds of thousands of interconnections among the different parts of the system, our solution has been proven to significantly reduce the design lead time from weeks to hours in real-world test cases.

I/O Planning & Optimization
one or more chip in a level

More efficient system design turns down manufacturing costs while improves performance and reliability of the final electronic product. HIPER comes as the “missing piece of the EDA puzzle” needed to complete the 2.5D-IC and 3D-IC design flow.

The video shows a quick preview of a HBM-based 2.5D-IC system optimization.