GENIO Overview

Today, more and more semiconductor applications are driving highly complex solutions that require integrating multiple functionalities, high-speed processing and an enormous amount of data storage.

As a result, single-chip integration has become technically challenging and economically impractical. Why?

• Big data is exploding, requiring more computing resources and I/O components
• Transistor sizes are fast reaching their physical reduction limits that caps the single-chip achievement of “Moore law”
• IC complexity is expanding exponentially and with it, skyrocketing IC design costs

What’s required is a new level of physical integration that continues meeting the promise of cope Moore’s law.  In other words, new innovative ways to put multiple chips together in an ever-shrinking foot print.

Heterogeneous integration is the semiconductor industry’s answer.  But that solution brings with it a whole new set of design challenges.

• Overcoming diverse silicon and package technologies
• Accommodating high-speed interconnection demands for IC/packaging co-design capabilities
• Implementation and analysis across different engineering domains
• Complete, consistent model across tool platforms.

What’s needed is revolutionary EDA solution.  A single, integrated tool that supports all current and future IC and package EDA design platforms. In other words, the missing piece of the EDA puzzle; an EDA tool that completes next generation system designs, gives a differentiating edge to existing solutions and provides faster, lower cost and system optimization.

Meet he GENIO^TM product family, the first truly integrated from the ground up EDA IC/packaging co-design tools. GENIO™ provides a holistic design environment that ensures design efficiency.  In other words, fast time-to-design, fast-time-to production, fast time-to-market and faster time-to-success.

GENIO’s holistic design environment overcomes the twin challenges of integrating diverse silicon and package technologies and coupling them with high-speed interconnections in an elegant, efficient design.

It drives the design from concept to design First Time Right silicon success through system level exploration across architectures.

GENIO^TM provides chiplets/die, silicon interposer, package, and surrounding PCB co-design features that achieve area, power, and performance targets. It’s technology agnostic and seamlessly integrates through standard formats with all the existing commercial implementation platforms or to custom EDA flows through dedicated plug-ins.

GENIO’s co-design features include:

• An integrated environment across all platforms used for implementation and analysis of digital die, analog die, package, and PCB design
• A single, consistent interconnect manager that represents and maintains the interconnect model of the entire system that – replaces the error-prone spreadsheet exchange between engineering team
• A unique Cross-Hierarchical 3D-aware pathfinding engine that identifies the best interconnect in a 3D space. It optimizes hundreds of thousands of connections while reducing the number of physical resources needed for implementation.

Check out the entire GENIO Family on the following pages.