Today, more and more applications – Internet of Things, Automotive, Webscale, Artificial Intelligence, Machine Learning, Network Processors, Telemedicine – are driving for highly complex solutions which require the integration of multiple functionalities, high-speed processing and storing of enormous amount of data.

The traditional integration into a single piece of silicon has become technically challenging and economically not more viable.  The technology evolution opens the door to a new level of integration able to cope with Moore’s law: new sophisticated ways to put chips together with wafer-level packaging options, interposers for 2.5D integration, and outright 3D chip stacking.

Heterogeneous integration is the new terrain the industry is moving but the diverse nature of silicon and package technologies and the use of high-speed interconnections demands for major enhancements in co-design capabilities, to enable planning, implementation and analysis across different engineering domains as well as to provide a complete, consistent model across tool platforms.

The communication among the compute, memory, interface, sense, actuate components is going to play a fundamental role in the feasibility itself of the final system. In other words, I/O resources planning and optimization is a critical step for any design implementation flow and for its efficient and timely implementation.

Here comes our revolutionary solution GENIO: it coexists with all the existing IC and package EDA design platforms. It comes as an add-on to cover the “missing piece of the EDA puzzle” needed to complete next generation system designs, giving a differentiating edge with respect to existing solutions to provide a faster, lower cost and optimized solution.

How to leverage 2.5D features? Creating a new abstraction level, in which the system is split into multiple die (stacked or placed side by side), laid onto a Silicon Interposer or onto a Package or a combination of these.

For instance, a Silicon Interposer can host a large number of die-to-die connection, allowing an increase of I/O ports density. 2.5D-IC can thus provide enhanced system performance, reduce power consumption and support heterogeneous die integration.


Our road to complex system integration

The GENIO product family provides a holistic design environment to overcome the system integration challenges coming from the diverse nature of silicon and package technologies and the use of high-speed interconnections, with the final goal of ensuring design efficiency.

It drives the designer from concept to design First Time Right, avoiding entering “dead-end” architectures/design roads by enabling system level exploration across architectures to identify the more efficient & cost effective one.

It provides chiplets/die, silicon interposer, package, and surrounding PCB co-design features that are key to achieve the area, power, and performance targets, without being overwhelmed by the complexity of the system interconnect. It has been designed to be technology agnostic and to seamlessly integrate with all the existing commercial implementation platforms (via standard formats) or custom EDA flows (through dedicated plug-ins).

To enable planning, implementation and analysis across different engineering domains as well as to provide a complete, consistent model across tool platforms the GENIO product family will add key co-design features:

  • An integrated environment providing the system model across the platforms used for implementation and analysis of digital die, analog die, package, and PCB portions. The data representation between GENIO and each platform is bidirectional and brings a direct integration with the platform to exchange the planning and implementation data
  • A single, consistent interconnect manager able to represent and maintain the interconnect model of the entire system – connectivity between silicon die micro-bumps, interposer routes/vias, through-silicon vias, and package bumps – replacing the error prone process of spreadsheet exchange between engineering team
  • A unique Cross-Hierarchical 3D-aware pathfinding engine able to identify the best interconnect in a 3D space, driven by physical and electrical design constraints. It automates the optimization of up to hundreds of thousands of connections while reducing the number of physical resources needed for implementation
Cross-Hierarchical Optimization (CHO)

GENIO 3D-aware pathfinding engine enables interconnect optimization across a complete 3D system architecture. Groups of signals can be cross-highlighted in the Connectivity, Nets and Pins panels, while displayed in the 2D and 3D canvas.

Cross-Hierarchical Optimization
GENIO Cross-Hierarchical Optimization
Design Constraints

GENIO “What & Where” metodology facilitate driving the system interconnect optmization. Pin Groups can be created across the system stack to drive the optimization in selected areas. Signal Groups are automatically genereted by the CHO, after optimization, to collect signals assigned to Pin Groups.

Physical and electrical design constraints
GENIO physical and electrical design constraints