In the new era of function intensive IC-design, more and more applications are driving for highly complex solutions, requiring the adoption of HBM based 2.5D heterogeneous systems.

GENIO 2.5D optimize the interconnect of these systems, which include  chiplets, high-bandwidth memory technologies such as HBM / HBM2 requiring a wide communication bus interconnected on a silicon interposer with large numbers of I/Os.

Key Features
  • GENIO 2.5D provides a common, cross-fabric, environment to represent all the levels of the 2.5D systems including one or more die, silicon interposer, package and even PCB portions along with design constraints
  • Multi level stacks are supported and multiple components can be seated in each level
  • Silicon Interposer friendly: GENIO2.5D delivers an automation to help designers to create a floor-planning aware SI component and make it ready for back annotation to Place & Route tools
  • A GUI (Graphic User Interface) facilitate the designer to create from scratch, import or incrementally update all the cross-fabric structures to be stored in a common system database. The tool efficiently allows the designer to create, explore, optimize and dynamically modify different system configurations
  • GENIO 2.5D eliminates all the lengthy and error prone manual activities associated with the management of complex, horizontal and vertical, interconnects allowing the system designers to  focus on the aspects of “what if” analysis and early feasibility studies, avoiding to enter “dead-end” architecture
  • GENIO 2.5D patented cross-hierarchical 3D aware  pathfinding optimization methodology, enables end-to-end interconnect optimization across the entire system hierarchy, in one single design cycle
  • GENIO 2.5D coexists with the existing IC and package EDA design platform
  • GENIO 2.5D includes “SMART” TSV placement and assignment. By optimising the TSV matrix and reducing the TSV resources needed the system design can be optimised in order to minimise manufacturing cost and maximise production yields
TSV management and optimization

Through Silicon Vias (TSV) can be placed in the Silicon Interposer to become part of the vertical system interconnect. GENIO 3D minimize the overall number of TSV needed and optimize the system interconnect: unused TSVs are discarted while the used ones are back annotated for physical implementation.


GENIO 2.5D product may include 2 optional features: I/O Ring Builder and RDL feasibiity router.

Option 1  -  I/O Ring Builder

I/O rings can be automatically generated using a pattern-based methodology.

Option 2  - RDL feasibility router

One-layer feasibility router facilitate in-chip exploration of many different bumping configurations.

Design Methodologies
  • Using GENIO 2.5D the designer can execute a “Whiteboard flow”, developing a system from initial rough data to create a well-enough seed for 2.5D-IC physical implementation.
The "Whiteboard Flow"

GENIO 2.5D delivers a “Whiteboard Flow” to support the Silicon Interposer creation based on the configuration of the objects seated on its top side. This innovative, floorplanning aware, methodology drastically reduces the number of physical resources needed, TSVs and connections, bringing several advantages at the manufacturing stage.

floorplanning aware
  • System design data may be entered on the fly in an arbitrary order as it becomes through the design process.
  • GENIO 2.5D provides an environment for the designer to build more than one 2.5D floor plan and after optimization to make a comparison between the different results.
  • The platform supports Top-down, Bottom-up or Mixed design flows.
  • GENIO 2:5D complete flexibility by supporting pre-configured components such as HBM2 or a full/partial assignment of package ball-out, or full/partial assignment on ICs.
  • The optimization is constraint driven: user can fine tune standard constraints and/or create custom, project specific, ones.