The Challenge

Nowadays, the microelectronics market foresees 5 growth vectors – Internet of Things, Automotive, Webscale, AI/Machine Learning, China. All these vectors will require high-speed processing and storing of enormous amount of data. Currently we face 2 major challenges:

  1. The continuous transistor scaling is becoming technically and physically not feasible. Further scaling and integration into a single IC is challenging not just about physics (in latest technology node transistors are approaching the size of atoms) but mainly about economics. The cost-effectiveness seems to have hit a sweet spot at about 28nm;
  2. Memory data throughput needs innovation to match the increasing processors’ performance. This requires the adoption of high-bandwidth memory technologies such as HBM / HBM2 implying a wide communication bus.

The Strategy

To overcome all these issues, the industry is looking at 2.5D & 3D integration which represent the emerging alternative to transistor scaling. It consists in creating a new level of abstraction, in which the system is divided into multiple silicon components either stacked on top of one another, or placed side-by-side onto a silicon interposer or in a package, or hybrid combinations of the previous solutions. The communication among the compute, memory, interface, sense, actuate components is going to play a fundamental role in the feasibility itself of the final system.

How to leverage 2.5D & 3D features? Creating a new abstraction level, in which the system is split into multiple die (stacked or placed side by side), laid onto a Silicon Interposer or onto a Package or a combination of these.

For instance, a Silicon Interposer can host a large number of die-to-die connection, allowing an increase of I/O ports density. 2.5D-IC can thus provide enhanced system performance, reduce power consumption and support heterogeneous die integration.

In other words, I/O resources planning and optimization is a critical step for any 2.5D & 3D microelectronic design implementation flow and for its efficient and timely implementation.

New methodologies and design automation tools are required in order to widespread the use of this approach.

Our Solution

Monozukuri has developed  HANOI®, a disruptive co-design platform, to support and automate system-level architectural explorations, floorplanning and I/O Planning in complex 2.5D & 3D heterogeneous systems (many different components and/or very high interconnect complexity) where manual connectivity optimization of tens of thousands of wires is a lengthy and error prone activity. An automated solution is required to shorten time to market.

The Hanoi Platform

  • provides package, silicon interposer and die co-design features that are key to achieve the area, power and performance targets, without being overwhelmed by the complexity of dealing with horizontal and vertical interconnects
  • thanks to standard format Hanoi can be integrated with all the existing commercial EDA platforms
  • plug-in mechanism allows easy integration with custom flows/tools
  • deals with system constraints, both ways: top-down (die-driven) and bottom-up (package-driven)
  • offers an I/O optimization interface from which the cross-fabric communication structures can be created and optimized
  • allows the designer to explore several different configurations and select the best one in order to reduce the total wire length and crossings (what-if analysis)
  • brings extreme flexibility as its optimization algorithms can be customized according to the specific design requirements

HANOI provides a common, cross-fabric, environment to represent all the levels of the 2.5D and 3D system design components (one or more die, silicon interposer, package and even PCB portions) and design constraints. Free from all the lengthy and error prone manual activities, the system designers can focus on the aspects that are key to carry out “what if” analysis and early feasibility studies, avoiding to enter “dead-end” architecture. The goal of first time right design, without being overwhelmed by the complexity of dealing with horizontal and vertical interconnects, is in reach.

A GUI (Graphic User Interface) is available to the designer. From there the cross-fabric structures can be imported or created from scratch and stored in a common database. Thanks to its speed and automation functionalities, HANOI facilitates the designer to create, explore, optimize and compare different floorplanning, and dynamically modify and store optimization results according to the final configuration.

The Hanoi GUI

The Hanoi "I/O Ring Builder"

HANOI delivers a “Whiteboard Flow” to support the Silicon Interposer creation based on the configuration of the objects seated on its top side. This innovative, floorplanning aware, methodology drastically reduces the number of physical resources needed, TSVs and connections, bringing several advantages at the manufacturing stage.

The Hanoi "Whiteboard Flow"

Our patented cross-hierarchical pathfinding optimization engine, enables a 3D-aware optimization, seeking for the best routing path across the entire system hierarchy, in one single run. The optimization is constraint driven: user can fine tune standard constraints and/or create custom, project specific, ones.

HANOI seamlessly integrate, via standard formats, with all the existing commercial physical implementation platforms. It brings extreme flexibility as its cross-hierarchical pathfinding optimization algorithms can be customized according to the specific design requirements. It coexists with the existing IC and package EDA design platform, and it comes as an add-on to cover the “missing piece of the EDA puzzle” needed to complete the 2.5D and 3D microelectronic systems design flow, giving a differentiating edge with respect to existing solutions.

HANOI open architecture enables new standard and customized features, to follow up new market needs and target specific proprietary customer’s requirements in separate releases.