GENIO 2D automates I/O planning, management and optimization from one or more ICs to package level. Using the tool designers can quickly and easily assemble complete cross-domain systems (ICs and package) and drive pin assignment and optimization through a rule-based methodology.
The environment enables the integration of single or multiple high-pin count chips into a wide variety of package configuration, and supports wire-bond, flip-chip or mixed assembly methods.
A drag-and-drop technique can be used to compose the system directly in the graphic system view.
With a common methodology, system architect can control the design from an IC-centric or package-centric perspective during early planning and prototyping or detailed implementation.

Key Features
  • GENIO 2D facilitates the seamless flow of data between different domains allowing changes to automatically propagate to adjacent components where their impact can be immediately evaluated. Feasibility functions provide the means to incorporate aspects of detailed implementation while still in the early stages of design planning. This ability to optimize the IO and connectivity design plan prior to detailed implementation will result in optimal performance, cost and manufacturability.
  • GENIO 2D facilitates device placement with associated pin and net assignments within the chip-package system prior to physical chip/package implementation, thus enabling upfront system optimization.
  • GENIO 2D creates and manages the physical relationship and hierarchy between components and displays the entire system or a selected subset in a single design view with fly-lines representing wire-bond/routing connectivity between components.
  • GENIO 2D Provides a 3D interactive preview of the complete assembled system.
  • GENIO 2D coexists with the existing IC and package EDA design platform.
Options

GENIO 2D product may include 3 optional features: Multi chip per level, I/O Ring Builder and RDL feasibiity router.

Option 1  - Multi chip per level

Enables the exploration and optimization of SiP and MCM systems.

Option 2  -  I/O Ring Builder

I/O rings can be automatically generated using a pattern-based methodology.

Option 3  -  RDL feasibility router

One-layer feasibility router facilitate in-chip exploration of many different bumping configurations.

Design Methodologies
  • Designers may interactively or semi-automatically build a partial or full I/O Plan of each IC component: number of I/Os on each IC side, number of Powers & Grounds required and their placement, placement of busses, placement of differential pairs, addition of special cells. Memory and IP can also be imported as read-only silicon components to be used as constraints during System optimization.
  • GENIO 2D enables the creation of new packages or the re-use of existing ones. An existing initial ball-out assignment can be taken into consideration or a new one generated automatically.
  • Multiple components from the different domains can be placed and connected to create the final System layout starting from either open data or spreadsheet. Different layout configurations can be explored, the pin-out optimization being based on the system floorplan, connectivity, and electrical constraints. Finally, the optimized I/O assignment of each single component can be back annotated to Place&Route tools and  Package design technology of choice.
  • A Rules Engine supports standard rules but also enables the user to customize assignment rules for both I/O Placement and Package ball-out during automatic creation and optimization.
  • System design data is entered in arbitrary order, as it becomes available during the design flow. GENIO 2D therefore provides value early during feasibility studies or early design planning and continues to add value throughout the full system design process, as the design becomes more refined.